The present invention relates to a power semiconductor device used as a high-voltage large-current device.
As a semiconductor device of this type, a device in which a power semiconductor component and a control semiconductor component for controlling driving of the power semiconductor component are integrated on a single semiconductor substrate has been mainly used along with recent developments in IC techniques.
FIGS. 10 and 11 show conventional power semiconductor devices of this type.
FIG. 10 shows a conventional power semiconductor device. Referring to FIG. 10, reference numeral 1 denotes an n-type crystalline Si (silicon) substrate with low resistivity; 2, 3, and 4, an n-type drain region, a p-type active region, and an n-type source region, respectively, of a high-voltage large-current vertical n-channel MIS (metal-insulator semiconductor) transistor; 5, 6, and 7, a gate-oxide film, a gate-electrode material, and a passivation-oxide film of the gate-electrode material, respectively, of the high-voltage large-current n-channel MIS transistor; 8 and 9, a source electrode and a drain electrode, respectively, of the high-voltage large-current n-channel MIS transistor; 10, 11, and 12, a p-type active region, an n-type source region, and an n-type drain region, respectively, of a low-voltage n-channel MIS transistor integrated to control the high-voltage large-current vertical n-channel MIS transistor; 13, 14, and 15, a gate-oxide film, a gate-electrode material, and a passivation-oxide film of the gate-electrode material, respectively, of the low-voltage n-channel MIS transistor; 16 and 17, a source electrode and a drain electrode, respectively, of the low-voltage n-channel MIS transistor; 18, 19, and 20, an n-type active region, a p-type source region, and a p-type drain region, respectively, of a low-voltage p-channel MIS transistor integrated to control the high-voltage large-current n-channel MIS transistor; 21, 22, and 23, a gate-oxide film, a gate-electrode material, and a passivation-oxide film of the gate-electrode material, respectively, of the low-voltage p-channel MIS transistor; 24 and 25, a source electrode and a drain electrode, respectively, of the low-voltage p-channel MIS transistor; 26, a p-type isolation region for electrically isolating the control low-voltage n-channel and p-channel MIS transistors from the high-voltage large-current vertical n-channel MIS transistor; and 27, an isolation-oxide film for electrically isolating the individual transistors. In power transistor configuration of the type shown in FIG. 10 and 11, the output of the control stage is coupled to the gate of the power transistor. The semiconductor device having the above arrangement is disclosed in, e.g., a known literature (1987 IEEE International Electron Devices Meeting [C. Contiero et al., "Design of A High Side Driver in Multipower-BCD and Vipower Technologies.," 1987 IEEE IEDM Technical Digest, p-p. 766-769]).
The above semiconductor device, however, has the following two drawbacks.
First, when the high-voltage large-current vertical n-channel MIS transistor is driven and the drain region 2 operates in a low-voltage linear region, a parasitic PNPN component is formed through, e.g., a path of p-type source region 19 .fwdarw. n-type active region 18 .fwdarw. p-type isolation region 26 .fwdarw. n-type drain region 2 .fwdarw. n-type source region 4, and an abnormal current caused by latch-up flows. A parasitic PNPN component is also formed through a path of p-type source region 19 .fwdarw. n-type active region 18 .fwdarw. p-type active region 10 .fwdarw. n-type source region 11 and driven in from off-state to on-state by an external noise pulse, thereby causing so-called latch-up. For this reason, an abnormal large-current flows through the above path. In this case, the current flowing through the former PNPN component is an abnormal current generated between the control low-voltage p-channel MIS transistor and the high-voltage large-current n-channel MIS transistor, and the current flowing through the latter PNPN component is an abnormal current generated between the control low-voltage p-channel MIS transistor and the control low-voltage n-channel MIS transistor. These abnormal currents cannot be eliminated unless a supply voltage to the semiconductor device is stopped. If the abnormal currents are allowed to flow, they result in permanent loss of circuit function of the semiconductor device.
In addition, the high-voltage large-current vertical n-channel MIS transistor and the control low-voltage n- and p-channel MIS transistors are isolated by a PN junction formed by the p-type isolation region 26 and the n-type drain region 2. Since an isolation voltage realized by this junction is at most 200 V, a voltage which can be applied to the drain electrode 9 of the high-voltage large-current n-channel MIS transistor is limited to 200 V. That is, in the semiconductor device having the arrangement shown in FIG. 10, it is difficult to integrate a high-voltage large-current vertical n-channel MIS transistor having a voltage exceeding 200 V.
In order to eliminate the above drawbacks, a semiconductor device has been proposed in which control low-voltage n- and p-channel MIS transistors and a high-voltage large-current vertical n-channel MIS transistor are isolated by a thick insulating film so that an isolation voltage between each two transistors is improved and no parasitic PNPN component is formed between the two transistors.
FIG. 11 shows a semiconductor device for eliminating the above drawbacks. Referring to FIG. 11, reference numeral 28 denotes an n-type crystalline Si substrate with low resistivity; 29, 30, and 31, an n-type drain region, a p-type active region, and an n-type source region, respectively, of a high-voltage large-current vertical n-channel MIS transistor; 32, 33, and 34, a gate-oxide film, a gate-electrode material, and a passivation-oxide film of the gate-electrode material, respectively, of the high-voltage large-current vertical n-channel MIS transistor; 35 and 36, a drain electrode and a source electrode, respectively, of the high-voltage large-current vertical n-channel MIS transistor; 37, 38, and 39, a p-type active region, an n-type source region, and an n-type drain region, respectively, of a low-voltage n-channel MIS transistor integrated to control the high-voltage large-current n-channel MIS transistor; 40, 41, and 42, a gate-oxide film, a gate-electrode material, and a passivation-oxide film of the gate-electrode material, respectively, of the low-voltage n-channel MIS transistor; 43 and 44, a source electrode and a drain electrode, respectively, of the low-voltage n-channel MIS transistor; 45, 46, and 47, an n-type active region, a p-type source region, and a p-type drain region, respectively, of a low-voltage p-channel MIS transistor integrated to control the high-voltage large-current n-channel MIS transistor; 48, 49, and 50, a gate-oxide film, a gate-electrode material, and a passivation-oxide film of the gate-electrode material, respectively, of the low-voltage p-channel MIS transistor; 51 and 52, a source electrode and a drain electrode, respectively, of the low-voltage p-channel MIS transistor; 53, 54, and 55, isolation-oxide films for dielectrically isolating the individual transistors; and 56, a polycrystalline Si layer, buried between the isolation-oxide films 55, for realization of a planar surface.
The semiconductor device having the above arrangement is disclosed in, e.g., a known literature (1987 IEEE Custom Integrated Circuits Conference [Y. Ohata et al., "Dielectrically Isolated Intelligent Power Switch," Proceedings of the IEEE 1987 Custom Integrated Circuits Conference, p-p. 443-446]).
FIGS. 12a to 12g show a method of manufacturing the semiconductor device shown in FIG. 11. This method will be described below with reference to FIGS. 12a to 12g. As shown in FIG. 12a, an oxide film 54a is formed on the surface of an n-type crystalline Si substrate 28 with low resistivity. As shown in FIG. 12b, an oxide film 54b is formed on the surface of an n-type crystalline Si substrate 45a. Thereafter, as shown in FIG. 12c, the oxide films 54a and 54b are brought into contact with each other and heated up to a high temperature to react with each other, thereby forming one oxide film 54. As shown in FIG. 12d, the n-type crystalline Si substrate 45a, the isolation-oxide film 54, and the n-type crystalline Si substrate 28 are partially removed by an RIE (Reactive Ion Etching) method. As shown in FIG. 12e, an n-type crystalline Si region 29a having a predetermined thickness is formed by epitaxial growth in a region removed by the RIE method. Subsequently, lapping and surface polishing are performed from the n-type crystalline silicon substrate 45a and the n-type crystalline Si region 29a to set a thickness T of the n-type crystalline Si substrate 45a to about 20 .mu.m, thereby forming an n-type active region 45 of a low-voltage p-channel MIS transistor and an n-type drain region 29 of a high-voltage large-current n-channel MIS transistor. As shown in FIG. 12g, the n-type active region 45 is partially removed by the RIE method until the underlying isolation-oxide film 54 is exposed, thereby forming a trench. Inner walls of the trench are oxidized to form isolation-oxide films 55. Thereafter, for realization of a planar surface, a polycrystalline Si layer 56 is filled in a trench surrounded by the isolation-oxide films 54 and 55. Subsequently, a p-type active region 37 of a low-voltage n-channel MIS transistor is formed. A high-voltage large-current n-channel MIS transistor is formed in the n-type drain region 29, and control low-voltage n- and p-channel MIS transistors are formed in the p- and n-type active regions 37 and 45, respectively, thereby completing the semiconductor device shown in FIG. 11.
According to the semiconductor device shown in FIG. 11, the high-voltage large-current n-channel MIS transistor and the control low-voltage n- and p-channel MIS transistors are isolated dielectrically by the isolation-oxide films 54 and 55. Therefore, latch-up through the path of p-type source region 19 .fwdarw. n-type active region 18 .fwdarw. p-type isolation region 26 .fwdarw. n-type drain region 2 .fwdarw. n-type source region 4, which is problematic in the semiconductor device shown in FIG. 10, can be eliminated.
In addition, by sufficiently increasing the thickness of the isolation-oxide films 54 and 55, an isolation voltage exceeding 200 V, which cannot be realized by junction isolation, can be easily achieved. Therefore, a high-voltage large-current n-channel MIS transistor with a voltage exceeding 200 V can be integrated.
In the conventional semiconductor device having the arrangement shown in FIG. 11, however, the low-voltage n-channel MIS transistor and the low-voltage p-channel MIS transistor are isolated by the PN junction constituted by the p-type active region 37 and the n-type active region 45. Therefore, for example, a parasitic PNPN component is formed through a path of p-type source region 46 .fwdarw. n-type active region 45 .fwdarw. p-type active region 37 .fwdarw. n-type source region 38. That is, the above problem of latch-up is not completely solved. In order to disconnect this path, the low-voltage n- and p-channel MIS transistors must be completely isolated from each other by an insulating film such as an oxide film. In order to achieve this isolation, the boundary region between the n-type active region 45 and the p-type active region 37 must be removed by the RIE method to form a trench and an insulating film must be filled in the trench, as in the method of forming the isolation-oxide film 55 described with reference to FIG. 12g. As described above with reference to FIG. 12f, however, the n-type active region 45 is thick, i.e., has a thickness of about 20 .mu.m. Therefore, in order to form a trench having a depth of 20 .mu.m, the trench must be widened to have a width of about 8 .mu.m. For this reason, if the low-voltage n- and p-channel MIS transistors are isolated by an insulating film, these MIS transistors cannot be integrated at high packing density. On the contrary, it can be easily assumed that in order to achieve a high packing density, the thickness of the n-type active region 45 can be further decreased to decrease the depth of the trench, thereby narrowing the isolation region. As described above with reference to FIG. 12f, however, the thickness of the n-type active region 45 is adjusted by lapping and surface polishing. Therefore, since a lapping and surface polishing precision is limited, it is difficult to control the thickness of the n-type active region 45 to several .mu.m or less throughout the entire surface of, e.g., a 4-inch diameter semiconductor substrate.
The above conventional drawbacks can be summarized as follows.
(i) In the conventional arrangement shown in FIG. 10, all of the high-voltage large-current n-channel MIS transistor and the control low-voltage n- and p-channel MIS transistors are isolated by the PN junction. Therefore, parasitic PNPN components are formed between the high-voltage large-current n-channel MIS transistor and the control low-voltage p-channel MIS transistor and between the control low-voltage n-channel MIS transistor and the control low-voltage p-channel MIS transistor, respectively, thereby producing latch-up. In addition, since the isolation voltage of the PN junction is limited, a high-voltage large-current n-channel MIS transistor with a voltage exceeding 200 V cannot be integrated.
(ii) In the conventional arrangement shown in FIG. 11, a parasitic PNPN component is formed between the control low-voltage n-channel MIS transistor and the control low-voltage p-channel MIS transistor, thereby causing latch-up. In order to suppress this latch-up and integrate the control low-voltage n- and p-channel MIS transistors at high packing density, the thicknesses of the p-type active region 37 and the n-type active region 45 constituting the low-voltage n- and p-channel MIS transistors need only be decreased. Since, however, the thicknesses of these active regions are adjusted by lapping and surface polishing, it is difficult to form thin layers.